The present invention relates generally to the field of data communication. More particularity, the present invention discloses a fundamental building block of Current Mode Logic (CML)-based transistor circuit for an electronic circuit system for optical communication capable of running at an input clock frequency of 50 GHz (Gegahertz, 1 Gegahertz=109 cycles/sec) when implemented on Silicon with a 0.18 xcexcm CMOS wafer process. Thus, its direct applications include many subsystem functions such as flip-flops, dividers, counters, frequency multipliers, frequency synthesizers, multiplexers, demultiplexers, phase and frequency detectors, Phase Locked Loops (PLL) in an optical switch IC for optical communication. Additional related applications are: Optical communication at 2.48 Gbit/sec (OC48) and 40 Gbit/sec (OC768) data rate, Gigabit Ethernet, 10 Gigabit Ethernet, Blue Tooth technology (2.4 GHz) and wireless LAN (5.2 GHz). At such a high data rate, the hardware infrastructure for a multimedia information super highway is also enabled.
Optical Fiber has been used in voice and data communication for some time now due to its high bandwidth and excellent signal quality resulting from its immunity to electromagnetic interference. The inherent optical data rate from a modulated single-mode laser beam travelling through an optical fiber is expected to well exceed 1000 Gbit/sec.
To keep up with the data rate of optical data communications, the associated signal processing IC (Integrated Circuit) need to operate in the multiple GHz to hundreds of GHz range of clock frequency. Maskai et al published fully differential CMOS folded source-coupled gate circuit topologies using a series-gating technique of up to three levels of complexity (Synthesis Techniques for CMOS Folded Source-Coupled Logic Circuitsxe2x80x94Sailesh R. Maskai, Sayfe Kiaei, and David J. Allstot, IEEE Journal of Solid-state Circuits, VOL. 27, NO. 8, August 1992). Sharaf et al published a circuit topology of series-gated CML-based Bipolar circuits of up to two levels of complexity wherein the top level section includes a resistive load (Analysis and Optimization of Series-Gated CML and ECL High-Speed Bipolar Circuitsxe2x80x94Khaled M. Sharaf and Mohamed I. Elmasry, IEEE Journal on Solid-State Circuits, Vol. 31, No. 2, February 1996). Razavi et al published a circuit topology of one level CML-based CMOS circuits for optical communications wherein the load section includes a series connection of a resistor and a resonance inductor (A 10 Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detectionxe2x80x94Jafar Savoj, Behzad Razavi, 2001 IEEE International Solid-State circuits Conference, 2001). To further improve the performance parameters of such high speed circuits, the inclusion of a more general type of inductive components properly designed for RF (Radio Frequency) operation is a possibility.
The present invention is directed to a fundamental building block of 2-level series-gated CML-based transistor circuit incorporating a more general type of inductive components that include transformers and individual inductors for an electronic circuit system for optical communication. While the effect of resonance would naturally take place between an added inductive component and its equivalent node capacitance, Ceq, the inductance value of the added inductive component is further adjusted to achieve an optimized performance in the presence of any nonlinear behavior of the circuit and, especially, additional feedback effect in cases where the inductive components are coupled with each other to form a transformer.
The first objective of this invention is for the 2-level series-gated CML-based transistor circuit of the present invention to achieve a higher operating frequency.
The second objective of this invention is for the 2-level series-gated CML-based transistor circuit of the present invention to achieve a higher load-driving capacity while under a significant capacitive loading at its output.
Other objectives, together with the foregoing are attained in the exercise of the invention in the following description and resulting in the embodiment illustrated in the accompanying drawings.